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Patent Number: |
7485908 |
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Case ID: |
0 |
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Patent Title:
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Insulated gate silicon nanowire transistor and method of manufacture
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Status: |
ACTIVE |
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Status Date: |
2/3/2010 1:52:18 PM |
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Issue Date:
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2/3/2009 |
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Filed Date:
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8/18/2005 |
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Serial #:
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1/208,127 |
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Assignee Name:
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United States of America as represented by the Secretary of the Air Force
(Washington,
DC)
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Inventor(s):
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Anwar, Abul F , Webster, Richard T. |
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FIELD OF THE INVENTION
The present invention relates generally to transistor structures and, more particularly, to an insulated gate silicon nanowire transistor structure.
BACKGROUND OF THE INVENTION
As is known, free-standing nanostructures are currently being extensively explored. These nanostructures are especially attractive for sensor applications because their high surface-to-volume ratio makes them very sensitive to charged species
adsorbed on their surfaces. Lateral growth of carbon nanotubes between two electrodes during chemical vapour deposition (CVD) has been realized for which a lateral electric field applied between the electrodes attracts the growing nanotube towards the
counter-electrode. Although the potential of carbon nanotubes for applications such as gas-sensing field-effect devices has been demonstrated, the difficulty of synthesizing only metallic or only semiconducting nanotubes and the difficulty of modifying
nanotube surfaces have li . . . . More |
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An insulated gate silicon nanowire transistor amplifier structure is
provided and includes a substrate formed of dielectric material. A
patterned silicon material may be disposed on the substrate and includes
at least first, second and third electrodes uniformly spaced on the
substrate by first and second trenches. A first nanowire formed in the
first trench operates to electrically couple the first and second
electrodes. A second nanowire formed in the second trench operates to
electrically couple the second and third electrodes. First drain and
first source contacts may be respectively disposed on the first and
second electrodes and a first gate contact may be disposed to be
capacitively coupled to the first nanowire. Similarly, second drain and
second source contacts may be respectively disposed on the second and
third electrodes and a second gate contact may be disposed to be
capacitively coupled to the second nanowir . . . . More |
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What is claimed is:
1. An insulated gate silicon nanowire transistor amplifier structure, comprising: a substrate formed of dielectric material; a patterned silicon material disposed on the
substrate and including at least first, second and third electrodes uniformly spaced on the substrate by first and second trenches; at least a first nanowire formed in the first trench and being operative to electrically couple the first and second
electrodes; at least a second nanowire formed in the second trench and being operative to electrically couple the second and third electrodes; first drain and first source contacts respectively disposed on the first and second electrodes and first gate
contact being capacitively coupled to the first nanowire; second drain and second source contacts respectively disposed on the second and third electrodes and second gate contact being capacitively coupled to the second nanowire; wherein the first
drain contact is coupled to receive current f . . . . More |
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